In contemporary memory technology, static random access memory (SRAM) cells may be constructed in various circuit configurations. These circuits are constructed in order to provide data retention capabilities while minimizing power requirements, current leakage and overall device size. Furthermore, the manufacturability of the circuit must be maximized. Consequently, it is desirable to construct a memory cell with a minimum number of components and designed to diminish the impact on integrated circuit fabrication difficulty. For each component within the cell, there is therefore also consideration of the component size and both internal and external interconnections to the component.
A typical contemporary SRAM cell is constructed in a 4T-2R configuration. The two resistances within this configuration may either comprise resistor elements or switched capacitors utilized in order to create an equivalent resistance. Although the 4T-2R cell is compact, the pass transistors constructed as a part of the cell are of critical size because the remaining transistors of the cell must be constructed in a size directly proportional to the size of the pass transistors. As a result, the selection of a predetermined size for the pass transistor necessarily defines a larger size for the remaining transistors within the cell. Thus, larger transistors and accommodating resistors must be included within the cell, thereby undesirably increasing device size and power requirements. Further, the large resistors require a large amount of resistance in a relatively small area thereby producing additional problems known in the art.
An alternative 4T-2R cell may be constructed utilizing switched capacitive resistances. This device requires a total of eight transistors in order to complete the cell configuration. Thus, the use of switched capacitive resistances requires a total of eight transistors with numerous interconnections to the gates, sources, and drains of these transistors. Each external interconnection requires contact to the device and consequently consumes more surface area on the device, and may also require difficult and aggressive interconnect fabrication processes. As a result, device sizes are increased along with device capacitance and other problems associated with excessive external interconnections.
Therefore, a need has arisen for a memory cell which includes a minimum number of devices and associated interconnections, consumes minimal power, and may be constructed within a small area.